The present invention relates to semiconductor devices and methods of manufacture, and more particularly to a method for manufacturing an improved metal oxide semiconductor (MOS) transistor having a thin channel.
Field effect transistors (FETs) are the basic building block of today""s integrated circuits. Such transistors can be formed in conventional substrates (such as silicon) or in the SOI layer of a silicon-on-insulator (SOI) substrate.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device, while maintaining the device""s electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize electrical performance of a device.
Thin channel silicon-on-insulator (SOI) devices having a thickness of about 50 nm or less are a promising option to further continue SOI complementary metal oxide semiconductor (CMOS) device scaling. Thin silicon channel devices provide a sharper-sub-threshold slope (measure of the abruptness of the switching of the device), high mobility (because the device is operated at a lower effective field) and better short channel effect control.
A disadvantage of thin silicon channel devices is that as the silicon-on-insulator (SOI) film is thinned the series resistance increases. One solution to the increasing series resistance inherent in thin channel devices is the use of an elevated source/drain region that may be formed by selective epitaxial Si growth.
In prior art thin channel devices, the extension implants are implanted prior to the formation of the raised source/drain regions; creating at least the following problems. First, by implanting the thin Si layer with a high dose/high energy implant, the Si crystal layer may be amorphized. Additionally, during activation of the source/drain regions, the anneal processing step causes recrystallization of the amorphous layer, which may result in the formation of polysilicon and the formation of defects to the extension region resulting in a higher resistivity. In addition, it is also difficult to clean the surfaces since p-type regions are formed due to electrochemical reactions where the p-type material has a greater affinity for oxide material. Epitaxial growth requires a clean surface having a substantial crystalline structure. Another problem with growing selective epitaxial Si on doped surfaces is that there is a significant difference in the thickness grown as a function of time for p-type Si compared to n-type Si. The thickness depends not only on the dopant type but also on the amount of dopant. The thickness of epitaxial silicon is difficult to control in a high volume manufacturing environment.
Prior art process schemes directed toward overcoming the thermal budget and growing epitaxial silicon on doped surfaces include a disposable spacer approach, which is complex and cost inefficient. More specifically, in some prior art thin channel devices a wide disposable spacer is utilized to grow the raised source/drain regions. High-energy implants are then conducted to form deep source/drain regions. Following the implants, the wide disposable spacer is removed and the extension regions are formed. A wide spacer is typically used to form the raised source/drain implants. Thus, the Si region under the spacer is of appreciable dimension and is at least as thin as the channel region. Therefore, the above described prior art process does not overcome the problem of the high resistance region outside the raised source/drain area.
In view of the state of the art mentioned above, it would be highly desirable to provide a method for forming thin channel silicon-on-insulator devices that overcome the above described disadvantages in conventional processing
The present invention provides an integration scheme in which the extension dopants are mainly contained in an oxide film during the raised source/drain growth process. Therefore, the extension implants do not experience excessive diffusion as a result of the thermal budget of the raised source/drain growth process. Another advantage of the present invention is that the selective epitaxial Si is grown on an intrinsic Si surface, therefore overcoming the growth rate problems associated with growing Si on doped surfaces.
In broad terms, the inventive method for forming thin channel silicon-on-insulator devices comprises:
providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material;
forming a conformal oxide film atop the structure;
implanting the conformal oxide film with a first dopant impurity to form a first dopant impurity region;
forming a set of spacers atop the conformal oxide film, said set of spacers are adjacent to said gate region;
removing portions of the conformal oxide film not protected by said set of spacers to expose a region of the semiconducting material;
forming raised source/drain regions on the exposed region of the semiconducting material;
implanting the raised source/drain regions with a second dopant impurity to form a second dopant impurity region; and
activating the first dopant impurity region and the second dopant impurity region, whereby source/drain and source/drain extension regions are formed in the semiconducting material.
Another aspect of the present invention is a method for forming multiple thin channel devices on a single substrate, utilizing conventional photoresist masking, comprising the steps of:
providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material;
forming a conformal oxide film atop the structure;
implanting the conformal oxide film with a first dopant impurity to form a first dopant impurity region, while blocking selected regions with a first blocking material;
removing the first blocking material and applying a second blocking material over the region implanted with the first dopant impurity;
implanting the conformal oxide film with a second dopant impurity and removing the second blocking material;
forming a set of spacers atop the conformal oxide film, said set of spacers are adjacent to said gate region;
removing portions of the conformal oxide film not protected by said set of spacers to expose a region of the semiconducting material;
forming raised source/drain regions on the exposed region of the semiconducting material;
implanting the raised source/drain regions with appropriate dopant impurities to form source/drain regions; and
activating the dopant impurities, whereby source/drain and source/drain extension regions are formed in the semiconducting material.
More specifically, the inventive method includes depositing a conformal oxide film over an entire wafer, including the gate region of the device. The conformal oxide film is then implanted with the appropriate dopant impurity. A dielectric film is then deposited atop the conformal oxide layer and etched to form a spacer structure. Following spacer formation, the doped conformal oxide film is removed from the regions outside the spacer to expose the underlying wafer surface by a wet etch process, preferably including hydrofluoric acid. A portion of the doped conformal oxide film underlies the spacer and remains on the sidewalls of the gate region. The structure is then annealed to diffuse the dopant from the remaining portion of the conformal oxide into the underlying semiconducting layer to form extension regions.
In an alternate embodiment, p-doped and n-doped oxide films may be deposited over the p-type and n-type regions respectively, using a block mask and etch process.
In broad terms, the inventive method of forming thin channel MOSFETS comprises the steps of:
providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material;
forming a doped conformal oxide film atop the structure;
forming a set of spacers atop the doped conformal oxide film, the set of spacers are adjacent to the gate region;
removing portions of the doped conformal oxide film, not protected by the set of spacers to expose a region of the semiconducting material;
forming raised source/drain regions on the exposed region of the semiconducting material;
implanting the raised source/drain regions with a dopant impurity to form a dopant impurity region; and
activating the doped conformal oxide film and dopant impurity region, whereby source/drain and source/drain extension regions are formed in the semiconducting material.
More specifically, the inventive method includes depositing a doped oxide film, being a P-type doped oxide film or N-type oxide film, atop a substrate having at least one gate region. The P-type doped oxide film may comprise boron silicate glass (BSG). The N-type oxide film may comprise arsenic silicate glass (ASG) and phosphorus silicate glass (PSG). A dielectric film is then deposited atop the conformal oxide layer and etched to form a spacer structure. Following spacer formation, the doped conformal oxide film is removed from the regions outside the spacer to expose the underlying wafer surface by a wet etch process, preferably including hydrofluoric acid. A portion of the doped conformal oxide film underlies the spacer and remains on the sidewalls of the gate region. A raised source/drain region is formed by growing selective epitaxial silicon followed by source/drain implantation. The structure is then annealed to diffuse the dopant from the remaining portion of the doped conformal oxide into the underlying semiconducting layer to form extension regions. The annealing process activates the source/drain regions at the same time.
Another aspect of the present invention includes a thin channel silicon-on-insulator device formed by the above-described method. In broad terms, the thin channel silicon-on-insulator device comprises:
a substrate having a semiconducting material atop an insulating layer;
a gate region atop a portion of the semiconducting material;
a doped oxide film conformal to at least a sidewall of the gate region and atop a portion of the semiconducting material;
a set of spacers located on a horizontal surface of the conformal oxide film that lies adjacent to the gate region; and
a raised source/drain region on either side of the gate region, where the raised source/drain region are separated from the gate region by the set of spacers.